library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CONV_STD_DIR is
    port(
         clk: in std_logic;
         Xstd: in std_logic;
	 		Ystd: in std_logic_vector(8 downto 0);
	 		Zstd: in std_logic_vector(8 downto 0);
	 		Ydir: out integer range 320 downto 0;
	 		Zdir: out integer range 320 downto 0
   	);
end CONV_STD_DIR;

-- Esto lo unico que hace es esta cuenta (si X>0):
--160+160*Y
--160-160*Z


architecture Convertir of CONV_STD_DIR is
begin
    process(clk)
    begin
      if rising_edge(clk) then
         if Xstd='0' then
            if Ystd(8)='0' then
               Ydir <= 160 + conv_integer(Ystd(7 downto 0));
            else
               Ydir <= 159 - conv_integer(not(Ystd(7 downto 0)));
            end if;
            if Zstd(8)='0' then
               Zdir <= 160 - conv_integer(Zstd(7 downto 0));
            else
               Zdir <= 161 + conv_integer(not(Zstd(7 downto 0)));
            end if;
		   end if;
		end if;
	end process;
end Convertir; 
